SR Flip Flop


Home NOT Gate AND Gate OR Gate XOR Gate Half-Adder Full Adder SR Flip Flop

SR Flip Flop
srflip.gif (2500 bytes)
Select An Input Value

An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the inputs are turned off.  This simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 (top output) and 1 (bottom output).  The reset input causes the opposite to happen (top = 1, bottom =0).  Once the outputs are established, the wiring of the circuit is maintained until S or R go high, or power is turned off to the circuit.

This is a simple model of how one bit of RAM can be perpetuated.  There are many issues not shown here such as timing inputs and synchronization, but the simplicity of the circuit gives you an idea of how RAM operates.